TR2018-105

A Real-time Architecture for Agile and FPGA-based Concurrent Triple-Band All-Digital RF Transmission


    •  Dinis, D., Ma, R., Shinjo, S., Yamanaka, K., Teo, K.H., Orlik, P.V., Oliveira, A., Vieira, J., "A Real-time Architecture for Agile and FPGA-based Concurrent Triple-Band All-Digital RF Transmission", IEEE Transaction on Microwave Theory and Techniques, DOI: 10.1109/TMTT.2018.2860972, Vol. 66, No. 11, pp. 4955-4966, August 2018.
      BibTeX TR2018-105 PDF
      • @article{Dinis2018aug,
      • author = {Dinis, Daniel and Ma, Rui and Shinjo, Shintaro and Yamanaka, Koji and Teo, Koon Hoo and Orlik, Philip V. and Oliveira, Arnaldo and Vieira, Jose},
      • title = {A Real-time Architecture for Agile and FPGA-based Concurrent Triple-Band All-Digital RF Transmission},
      • journal = {IEEE Transaction on Microwave Theory and Techniques},
      • year = 2018,
      • volume = 66,
      • number = 11,
      • pages = {4955--4966},
      • month = aug,
      • doi = {10.1109/TMTT.2018.2860972},
      • url = {https://www.merl.com/publications/TR2018-105}
      • }
  • MERL Contacts:
  • Research Areas:

    Communications, Signal Processing

Contiguous/Non-Contiguous Carrier Aggregation (CA) is one of the key features from 4G systems that is expected to be evolved within 5G technologies. Thus, there is a need for the development of flexible, agile and reconfigurable radio transceivers with a native support for the integration of multiple bands and multiple standards. All-Digital RF Transmitters have demonstrated promising potential to the design of nextgeneration RF transceivers. However, the simultaneous multiband transmission is still one of the key limitations of current approaches. To address this problem, this paper presents a fully digital and parallel architecture that enables the real-time design of agile and concurrent triple-band transmission. The proposed architecture is suitable for both Contiguous and Non-Contiguous CA scenarios, and considerably surpasses the state-of-the-art in terms of frequency agility, maximum spacing between bands, and aggregated bandwidth. To enhance the system performance, an extension to a multi-level architecture, based on the analog combination of pulsed waveforms, is also demonstrated. Both architectures (2- and 7-level) were implemented in a FieldProgrammable Gate Array (FPGA). Measurement results in terms of Signal-to-Noise Ratio (SNR), Error-Vector Magnitude (EVM) and Adjacent-Channel Power Ratio (ACPR) are presented and discussed. Implementation-I, the 2-level architecture presents a frequency agility from 0.1 to 2.5 GHz (with a frequency resolution of 4.88 MHz) with an aggregated bandwidth of 56.26 MHz. Implementation-II, the 7-level design presents a frequency agility from 0.1 to 2 GHz (with a frequency resolution of 3.906 MHz) with an aggregated bandwidth of 112.5 MHz.

 

  • Related News & Events

    •  AWARD   Former Intern Receives IBM Scientific Award Honorable Mention
      Date: January 16, 2019
      Awarded to: Daniel Dinis
      MERL Contact: Rui Ma
      Research Areas: Communications, Signal Processing
      Brief
      • Former MERL intern Daniel Dinis from University of Aveiro (UA), Portugal has received the 2018 IBM Scientific Award with Honorable Mention referring to the contributions on "Real-time Tunable Delta-sigma modulators for All-Digital RF Transmitters" in his Ph.D. study.

        The award-winning work includes research conducted under the supervision of Arnaldo Oliveira and José Neto Vieira, professors from the Department of Electronics and Information Technology (DETI) of the UA, as well as contributions made during Daniel's 7 month internship in 2017 at MERL.

        The ceremony for the presentation of the 28th IBM Scientific Prize took on January 16th, at the Noble Hall of the Superior Technical Institute. It was chaired by Marcelo Rebelo de Sousa, President of the Portuguese Republic.
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