TR2020-012

Ferroelectric memory field-effect transistors using CVD monolayer MoS2 as resistive switching channel


    •  Teo, Koon Hoo, "Ferroelectric memory field-effect transistors using CVD monolayer MoS2 as resistive switching channel", Tech. Rep. TR2020-012, Mitsubishi Electric Research Laboratories, Cambridge, MA, February 2020.
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      • @techreport{MERL_TR2020-012,
      • author = {Teo, Koon Hoo},
      • title = {Ferroelectric memory field-effect transistors using CVD monolayer MoS2 as resistive switching channel},
      • institution = {MERL - Mitsubishi Electric Research Laboratories},
      • address = {Cambridge, MA 02139},
      • number = {TR2020-012},
      • month = feb,
      • year = 2020,
      • url = {https://www.merl.com/publications/TR2020-012/}
      • }
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  • Research Area:

    Applied Physics


Ferroelectric field-effect transistors (FeFETs) have been considered as promising electrically switchable nonvolatile data storage elements due to their fast switching speed, programmable conductance, and high dynamic range for neuromorphic applications. Meanwhile, FeFETs can be aggressively shrunk to the atomic scale for a high density device integration, ideally, without comprising the performance by introducing two-dimensional (2D) materials. So far, the demonstrated 2D material-based FeFETs mainly rely on mechanically exfoliated flakes, which are not favorable for large-scale industrial applications, and FeFETs based on organic ferroelectrics typically show a large writing voltage (e.g., >620 V), making these types of memory devices impractical to be commercially viable. Here, we demonstrate that monolayer MoS2 grown by chemical vapor deposition (CVD) can be used as a resistive switching channel to fabricate FeFETs, in which the MoS2 channel is modulated by a hybrid gate stack of HfO2/ferroelectric HfZrOx thin films. The programming processes in the 2D MoS2 FeFETs originate from the ferroelectric polarization switching, yielding two distinct write and erase states for data storage and cumulative channel conductance for artificial synapse applications. Our 2D FeFETs show a low-voltage-driven feature (<63 V) and gate-tunable ferroelectric hysteresis characteristics. The thin HfO2 layer in the hybrid gate stack likely plays crucial roles in preserving the ferroelectricity of the device and lowering the threshold of switching voltages through energy redistribution. Our findings open an avenue for the use of CVD-grown layered materials as the resistive switching mediums combined with HfO2-based ferroelectrics for future energy-efficient “brain-on-a-chip” hardware.