Low Latency Decoding of EG LDPC Codes

    •  Zhang, J.; Yedidia, J.S.; Fossorier, M.P.C., "Low Latency Decoding of EG LDPC Codes", Journal of Lightwave Technology, Vol. 25, No. 9, September 2007.
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      • @article{Zhang2007sep2,
      • author = {Zhang, J. and Yedidia, J.S. and Fossorier, M.P.C.},
      • title = {Low Latency Decoding of EG LDPC Codes},
      • journal = {Journal of Lightwave Technology},
      • year = 2007,
      • volume = 25,
      • number = 9,
      • month = sep,
      • url = {}
      • }
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We describe simple interactive decoders for low-density parity check codes based on Euclidean geometries, suitable for practical VLSI implementation in applications requiring very fast decoders. The decoders are based on shuffled and replica-shuffled versions of iterative bit-flipping and quantized weighted bit-flipping schemes. The proposed decoders converge faster and provide better ultimate performance than standard bit-flipping decoders. We present simulations that illustrate the performance versus complexity trade-offs for these decoders. We can show in some cases through importance sampling that no significant error-floor exists.