We describe simple interactive decoders for low-density parity check codes based on Euclidean geometries, suitable for practical VLSI implementation in applications requiring very fast decoders. The decoders are based on shuffled and replica-shuffled versions of iterative bit-flipping and quantized weighted bit-flipping schemes. The proposed decoders converge faster and provide better ultimate performance than standard bit-flipping decoders. We present simulations that illustrate the performance versus complexity trade-offs for these decoders. We can show in some cases through importance sampling that no significant error-floor exists.