Low Power MBOFDM-UWB Transceiver Design
We investigated the power profile of the ECMA Multiband-OFDM standard compliant transceiver circuit. The research focused on the low-power, high speed FEC decoder. Our objective is to incorporate our research results into ASIC development.
Background & Objective: Multiband-OFDM has become the de facto technology for High data rate UWB and has been adopted as an ECMA standard. Due to the large bandwidth and high data rate, the average power consumption of current commercial UWB transceivers typically exceeds 400 mW. This is far from its potential ultra-low power consumption that UWB technology offers. Such high power consumption also limits the UWB technology from being used in certain applications such as in battery powered mobile nodes. The objective of this project is to provide the optimization in different design levels (network, algorithm, hardware architecture and circuit) and ultimately achieve a reduced total power consumption.
Technical Discussion: Our initial study generated the power profile for the transceiver baseband circuit. Our investigation shows that to achieve the maximum data rate of 480 Mbps, the power consumption and the size of the Viterbi decoder is expected to be more than 30% of the entire chip. We proposed two schemes that can lower the power adaptively based on the data rate of the received packet: a) Dynamic voltage scaling (DVS) in UWB receiver and b) Adaptive sliding block Viterbi decoder (ASDV). Both schemes exploit the variable data rate and the data packet structure in UWB standard. Using our proposed DVS design, we were able to achieve over 3X power saving at 55Mbps compared to a conventional design. We also compared the power and speed performance of different implementation options in individual components (e.g. Add-Compare-Select-Unit and Trace-Back-Unit) in the Viterbi decoder. The ASDV is an improve version of the sliding block Viterbi decoder that allows us to disable some portion of the circuit (and therefore save power) while still meet the throughput requirement.
Future Direction: We are working on low complexity/energy synchronization algorithm/architecture and cross-layer optimization of memory structure and other functional blocks.
Contacts:
Chunjie Duan
Jinyun Zhang
Technology Area: Digital Communications
Modification Date: October 24, 2007
