High Speed Data Acquisition
In system design and implementation of communication receivers, real data testing of the software models and prototypes is a critical step. This is due to the fact that propagation effects are complex and often difficult to model in software, and real data tests early on during system development stage help ensure a successful design. Further more, it is desirable to repeat same test conditions on models which undergo improvements. The high speed data acquisition device described in this project meets such a need. Originally designed for configurable ATV receiver demodulator development, it can be used for collecting data in other high speed transceiver development. A simplified version was prototyped in lab and used for universal modem system development. ATV: Advanced Television, IF: intermediate frequency, A/D: analog to digital converter, AGC: automatic gain control.
Background & Objective: This project was a part of the universal modem development. The primary objective was to provide a recorded real field data of several tens of seconds for testing the demodulator model and prototype performance. The device should be portable, easy to operate, and interface to a personal computer.
Technical Discussion: As shown in the above figure, analog signals from the low IF (5.38MHz) of the RF tuner are digitized by A/D and stored to on board memory. The sampling clock of the A/D is variable, determined by the System Control block. System Control also determines the start and stop of the acquisition process. Typically, over-sampling of factor of 2 to 4 of the base-band data rate maybe needed for digital timing recovery. For this development, the sample clock rate was chosen to be 21.52MHz. A 10-bit A/D (AD876 by Texas Instrument) was used. The analog gain of the input signal is controlled by the AGC block, which is set by System Control. The range of the input signal is limited within 2Vpp. Once the acquisition is completed, the data can be transferred via a PCI or parallel port to a permanent memory device or the host computer's hard disk drive. Various analog and digital interface connectors are available for monitoring and calibration purposes, as well as allowing alternative analog or digital inputs from different sources to be recorded. For the lab prototype, the System Control block is implemented in one Altera FPGA chip, and a SRAM module was used instead of DRAM. For designs which require longer data sequence, DRAM is more economical than SRAM. The DRAM controller was designed in one FPGA. A bus controller chip from Cirrus Logic was chosen for the interface to a PCMCIA portable hard disk. In the universal modem development, data collected in the lab are simply transferred to the host PC via digital I/O (provided by a CY233 interface chip), and later to Unix workstations for analysis.
Contact: Huifang Sun
Technology Area: Advanced Digital Television
Modification Date: August 2, 2004
